ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis by ACM-SIGDA

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Additional resources for ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings)

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Ever, the relatively small improvement in fidelity does not seem to justify the much greater computation that is required to search over solution topologies using Two-Pole as opposed to using the lineartime Elmore delay computation. 4 Near-Optimal Routing Trees We can solve the ORT problem optimally for any delay model using a backtracking enumeration of tree topologies with branch-and-bound pruning. Starting with a trivial tree containing only the source pin, we incrementally add one edge at a time to the growing tree.

Table 1 shows 8 examples, where 'exl' to 'exV' are from (4], 'ex8' is a general nonslicing floorplan topology (figure 5) with all module shape functions being ((1, 4), (2, 2), (4, 1)). The AOP1 row gives the results computed by our algorithm using floorplan hierarchies and AOP2 shows the results computed without hierarchies. Note that the actual number of realizations found by the algorithm is slightly larger than the number of bends on the curve listed in the table. This is due to the fact that the realisations have the same aspect ratio listed in the table, but different configurations.

In the Form-Tree procedure, each vertex and each edge are only visited once. This corresponds to a time complexity of O(Nt + N,) since the number of edges in the merged graph is not larger than that of the Pruned-graph. Conclusively, if W is the minimised weight, the time complexity for finding a tree in the bipartite graph is O(Nt) + (O(Nt) + O(Nt + N,)) * W. 4 PMS Realisation smaller than N and Nt is proportional to O(N), the The realisations of SPMSs and TPMSs are based on time complexity is thus linear with O(N * W).

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